In a semiconductor integrated circuit device, an internal signal is externally outputted through an output driver circuit. The output driver circuit is provided for driving an external circuit with a large current. FIG. 9 is a plan view showing a structure of a conventional representative output driver circuit. Referring to FIG. 9, an output driver circuit 1 comprises a first n channel MIS (Metal Insulator Semiconductor) transistor 2 and a second n channel MIS transistor 3. A gate electrode 4 of the first n channel MIS transistor 2 is connected to an input line 5 on a Low side of an internal circuit. A gate electrode 6 of the second n channel MIS transistor 3 is connected to an input line 7 on a High (Hi) side of the internal circuit. Source regions 8a of the first n channel MIS transistor 2 are connected to a ground line 9. Drain regions 10b of the second n channel MIS transistor 3 are connected to a power supply line 11. In addition, drain regions 8b of the first n channel MIS transistor 2 and source regions 10a of the second n channel MIS transistor 3 are connected to an output line 12.
Now, a sectional structure of the first n channel MIS transistor 2 will be described. FIG. 10 is a sectional view showing a structure of the first n channel MIS transistor 2 seen from the direction of a line X--X in FIG. 9. The gate electrode 4 is formed on a surface of a p-type silicon substrate 13 through a gate insulating film 14. The gate electrode 4 is continuously formed on the surface of the p-type silicon substrate 13 in a manner similar to zigzag fashion. (Referred to FIG. 9). Source and drain regions 8a and 8b of n-type impurity regions are alternately formed between straight portions of the gate electrode 4 on the surface of the p-type silicon substrate 13. The ground line 9 is connected to the source regions 8a. The output line 12 is connected to the drain regions 8b. A periphery of the gate electrode 4 is covered with an insulating film 15. In addition, surfaces of the insulating film 15, the ground line 9 and the output line 12 are covered with a surface protection film 16.
The second n channel MIS transistor 3 has the same sectional structure as that shown in FIG. 10. Thus, MIS transistors of the output driver circuit are formed such that the gate electrodes 4 and 6 are continuously routed on a plane, thereby increasing a gate width or a width of a channel formed under the gate of a transistor, so that current driving capability of the MIS transistor is enhanced.
Now, an operation of the output driver circuit will be described. FIG. 11 is an equivalent circuit diagram of the output driver circuit 1 shown in FIG. 9. Referring to FIG. 11, the first and the second n channel MIS transistors 2 and 3 are connected in series to each other. A drain region 10b of the second n channel MIS transistor 3 is connected to a power supply line 11. A source region 8a of the first n channel MIS transistor 2 is connected to a ground line 9. A gate electrode of the first n channel MIS transistor 2 is connected to an input line 5 on the Low side, and a gate electrode of the second n channel MIS transistor 3 is connected to an input line 7 on the Hi side. An output line 12 is connected to a connection portion between the two n channel MIS transistors 2 and 3.
First, when a positive voltage is applied from the input line 7 on the Hi side, the second n channel MIS transistor 3 is turned on, so that a power supply voltage V.sub.cc is outputted to the output line 12.
On the other hand, when a positive voltage is applied from the input line 5 at the Low side, the first n channel MIS transistor 2 is turned on, so that a ground potential is outputted to the output line 12. Since in the first and the second n channel MIS transistors 2 and 3, increased gate widths enhance the current driving capability, current amount externally inputted/outputted through the output line 12 can be increased.
In addition, the output driver circuit 1 also serves as an input protection circuit, which will be described in the following. For example, referring to FIG. 11, it is assumed that a positive over-current is applied from the side of the output line 12. In this case, a punch through phenomenon is caused between the source and drain regions of the first n channel MIS transistor 2 and the second n channel MIS transistor 3 so that a punch through current flows, whereby an over-current flows to the side of the power supply line 11 or to the side of the ground line 10, thus preventing the over-current from flowing to the side of the input lines 5 and 7 and protecting the internal circuit.
A function for protecting an input will be further described with reference to a result of an electrostatic breakdown test of input/output terminals of a semiconductor integrated circuit device. FIG. 12 is a schematic diagram of a test circuit employed in a testing method referred to as capacitor charging method. The capacitor charging method is a method of testing an electrostatic breakdown voltage of a semiconductor circuit by storing a charge in a capacitor through a direct current power supply, then discharging by means of switch the charge stored in the capacitor to a sample device (semiconductor integrated circuit) through a resistor. In the electrostatic breakdown test device, a resistance of a resistor R is 1.5 k.OMEGA. and a capacitance of a capacitor is 100 pf. FIG. 13 shows a sectional structure of the MIS transistor of the input driver circuit of the sample device (semiconductor integrated circuit). The MIS transistor shown in the drawing corresponds, for example, to a first n channel MIS transistor 2 of an output driver circuit. Numerals shown in the drawing indicate sizes of elements. A drain region 10b, a source region 10a and a gate electrode 7 are set to +12 V, 0 V and a floating state, respectively. In this state, a depletion layer is extended between the source and drain regions, so that a punch through current starts flowing. FIG. 14 is a diagram showing a potential distribution of MIS transistor. In FIG. 14, lines indicate equipotential lines. A voltage of a channel region under the gate gradually drops from 12 V on the side of the drain region 10b to 0 V on the side of the source region, wherein a punch through current flows. FIG. 15 shows a current density distribution in this state. It is understood from the drawing that a current flows under the gate.
When a negative over-current is applied from the side of the output line 12, it becomes a forward voltage to the p-type silicon substrate 13, so that a current flows in the substrate. Thus, the output driver circuit operates as an input protection circuit.
However, assuming that an additional over-current is applied, a drain voltage is raised, then the depletion layer is further extended and an electric field between the source and drain regions becomes a higher electric field. However, a ratio of the increase of amount of a punch through current is larger as compared with that of the extension of the depletion layer. As a result, the current density of the punch through current is increased. Then, when the current density of the punch through current is excessively increased, the punch through current does not sufficiently flow. Then, a high electric field is generated near the drain, so that the gate oxide film or a pn junction on the drain side is destroyed to generate a current path. This state is shown by arrows A and B in FIG. 13.
Although a target breakdown voltage for input/output terminals of a semiconductor integrated circuit is originally 3 kV, the electrostatic breakdown voltage of the above described MIS transistor was about 1.5 kV. As semiconductor integrated circuits are more highly integrated recently, a target breakdown voltage is not achieved in a miniaturized MIS transistor.
A similar problem occurs in a conventional input protection circuit of a semiconductor device, which will be described in the following. FIG. 19 is a circuit diagram of an input protection circuit. The input protection circuit comprises a single MIS transistor 30. A drain region 31 of the MIS transistor 30 is connected to a resistor 32 and a circuit 33 to be protected, and a source region 34 and a gate electrode 35 are connected to ground potentials 36 and 36.
FIG. 20 is a sectional view of a structure of the MIS transistor 30. The source region 34 and the drain region 31 are formed spaced apart on a major surface of a semiconductor substrate 38. A silicon oxide film 39 is formed on the major surface of the semiconductor substrate between the source and drain regions 34 and 31. Aluminum interconnection layers 40 and 41 are respectively connected to the source and drain regions 34 and 31. In addition, a part of the aluminum interconnection layer 41 connected to the source region 34 extends on an upper portion of the silicon oxide film 39 to form a gate electrode 35. An upper portion of the semiconductor substrate 38 is covered with an insulating film 42.
Now, an operation of a conventional input protection circuit will be described. Referring to FIG. 19 and 20, when an abnormally high voltage is applied to an input terminal 37, a high voltage is applied to the drain region 31 of the MIS transistor 30. The high voltage causes the punch through phenomenon between the source and drain regions, so that a current flows to the side of the ground potential 36 through the source region 34, thus preventing application of an abnormally high voltage to the side of the circuit 33 to be protected.
In the above described input protection circuit, a gate width of the MIS transistor 30 should be increased in order to improve an input breakdown voltage. However, due to miniaturization of a recent semiconductor device, a gate width cannot be increased, and the increase of a gate width results in prevention of miniaturization or high integration of the device.